GitHub - adibis/DDR2_Controller: DDR2 memory controller written in Verilog · GitHub

Name		Name	Last commit message	Last commit date
design		design
scripts		scripts
tb		tb
.denalirc		.denalirc
README.markdown		README.markdown
cds.lib		cds.lib
hdl.var		hdl.var
makefile		makefile

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I know I need a better description. It shall arrive once I have more time to spend on projects which do not need any time spent on them.

Enjoy!

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DDR2 memory controller written in Verilog

ddr hdl verilog verilog-project

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