design-compiler

2021 IC Design Contest geofence problem taken from RTL to a DRC/LVS-clean layout in TSMC 0.13 um (Design Compiler, IC Compiler II, PrimeTime, IC Validator), with a post-layout area/energy comparison of six variants

Projeto e síntese lógica de uma Unidade Lógica e Aritmética (ULA) parametrizável em SystemVerilog utilizando Synopsys Design Compiler (Tecnologia SAED32).

12th-order complex RLS self-interference cancellation Soft IP with FPGA prototyping, ASIC-portable RTL, ModelSim convergence and DC optimization evidence.

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

The RISCV project was converted from RTL code to GDS II format using 14nm PDKs. This was implemented with the ICC2 and Design Compiler NXT EDA tools from Synopsys, following a Flat Design Style

🎯 AI PPT Design Compiler — 从用户需求到可编辑 PowerPoint 的本地化演示文稿设计引擎。模块化页面渲染器、结构化 Schema、Design Planner、PPTX 输出。

Projeto introdutório de síntese lógica de uma porta AND em SystemVerilog utilizando o Synopsys Design Compiler com a biblioteca SAED32.

ETC10123 laboratory portfolio: SPI Master RTL, synthesis, Formality, ICC2 physical design, weekly labs, and release-backed reports.

ETC10122 coursework: dual-port RAM RTL, self-checking verification, ASIC-flow evidence, exercises, and a worked 2020 exam.

Functional Verification, ASIC Synthesis and Formal Verification of an AMBA Memory Interface Bridge integrated with the LEON3 Processor and GRETH Ethernet MAC.