icc2

数字后端设计专家 / Digital IC Physical Design Expert：12年+ 28nm–7nm 流片经验的 WorkBuddy 专家包。Netlist→GDS 实战问答：Floorplan、Placement/CTS、Routing 拥塞、STA setup/hold 收敛与 ECO、DRC/LVS、IR-drop/EM、UPF 低功耗；Innovus/ICC2/PrimeTime/Calibre/Voltus Tcl 命令与报错排查。

Extract embedded ICC color profiles from files

End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.

Headless IC Compiler II reference-NDM and design-library creation for a MIPS16 ASIC lab - nothing hardcoded, every stage self-verifies before trusting its own pass.

ETC10123 laboratory portfolio: SPI Master RTL, synthesis, Formality, ICC2 physical design, weekly labs, and release-backed reports.

ETC10122 coursework: dual-port RAM RTL, self-checking verification, ASIC-flow evidence, exercises, and a worked 2020 exam.

An RTL-to-GDSII ASIC Flow Project Design, simulate, synthesize, and layout a full 1×8 demux for 8-bit data — all the way from Verilog to GDSII.

ASIC Physical Design projects - RTL-to-GDSII on Synopsys ICC2 (18-macro & 6-macro blocks)